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M29W008ET M29W008EB
8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash Memory
FEATURES SUMMARY

Figure 1.
Package
ACCESS TIMES: 70ns, 90ns PROGRAMMING TIME: 10s per Byte typical PROGRAM/ERASE CONTROLLER (P/E.C.) - Embedded Byte Program Algorithm - Status Register bits and Ready/Busy Output 19 MEMORY BLOCKS - 1 Boot Block (Top or Bottom location) - 2 Parameter and 16 Main Blocks BLOCK, MULTI-BLOCK and CHIP ERASE MULTIPLE BLOCK PROTECTION/ TEMPORARY UNPROTECTION MODE ERASE SUSPEND and RESUME MODES LOW POWER CONSUMPTION - Standby and Automatic Standby modes 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION - Defectivity below 1ppm/year ELECTRONIC SIGNATURE - Manufacturer Code: 20h - M29W008ET Device Code: D2h - M29W008EB Device Code: DCh ECOPACK(R) TSOP40 PACKAGE
TSOP40 (N) 10 x 20mm

June 2005
Rev 0.1 1/43
www.st.com
1
M29W008ET, M29W008EB
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Address Inputs (A0-A19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Input/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Reset/Block Temporary Unprotect Input (RP) . . . . . . . . . . . . . . . . . . . . . . . . .11 VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Standard bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 3.2.2 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Protection and Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 4.2 4.3 4.4 4.5 4.6 4.7 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/43
M29W008ET, M29W008EB 4.8 4.9 4.10 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 5.2 5.3 5.4 5.5 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 7 8 9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Appendix A Block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Appendix B Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1 9.2 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3/43
M29W008ET, M29W008EB
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 19 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Write AC Characteristics, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Write AC Characteristics, E Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . 32 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Top Boot Block Addresses, M29W008ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Bottom Boot Block Addresses, M29W008EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Programmer Technique Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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M29W008ET, M29W008EB
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Addresses (Top Boot Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Addresses (Bottom Boot Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Write AC Waveforms, E Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . 32 Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 In-System Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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1 Summary description
M29W008ET, M29W008EB
1
Summary description
The M29W008E is a 8 Mbit (1Mb x 8) non-volatile Flash memory that can be read, erased at block, multi-block or chip level and programmed at Byte level. These operations are performed using a single 2.7V to 3.6V VCC supply voltage. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed using standard programming equipment. The memory is divided into blocks that are asymmetrically arranged. Both M29W008ET and M29W008EB devices have an array of 19 blocks composed of one Boot Block of 16 KBytes, two Parameter Blocks of 8 KBytes, one Main Block of 32 KBytes and fifteen Main Blocks of 64 KBytes. In the M29W008ET, the Boot Block is located at the top of the memory address space while in the M29W008EB, it is located at the bottom. The memory maps are showed in Figure 4: Block Addresses (Top Boot Block) and Figure 5: Block Addresses (Bottom Boot Block). Each block can be erased and reprogrammed independently so it is possible to preserve valid data while old data is erased. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. Erase operations in one block can be temporarily suspended in order to read from or program in blocks that are not being erased. Each block can be programmed and erased over 100,000 cycles. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. All previously protected blocks can be temporarily unprotected. In order to meet environmental requirements, ST offers this device in a TSOP40 (10 x 20mm) ECOPACK(R) package. ECOPACK(R) packages are Lead-free and RoHS compliant. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. The device is offered in package and supplied with all the bits erased (set to '1'). Table 1.
A0-A19 DQ0-DQ7 E G W RP RB VCC VSS NC
Signal Names
Address Inputs Data Input/Outputs, Command Inputs Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Supply Voltage Ground Not Connected Internally
6/43
M29W008ET, M29W008EB
Figure 2. Logic diagram
VCC
1 Summary description
20 A0-A19 W E G RP M29W008ET M29W00EB
15 DQ0-DQ7
RB
VSS
AI11359
Figure 3.
TSOP Connections
A16 A15 A14 A13 A12 A11 A9 A8 W RP NC RB A18 A7 A6 A5 A4 A3 A2 A1
1
40
10 M29W008ET 31 11 M29W008EB 30
20
21
A17 VSS NC A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 G VSS E A0
AI11360
7/43
1 Summary description
M29W008ET, M29W008EB
Figure 4.
Block Addresses (Top Boot Block)
M29W008ET Top Boot Block Addresses
FFFFFh 16 KByte BOOT BLOCK F0000h EFFFFh E0000h DFFFFh D0000h CFFFFh C0000h BFFFFh B0000h AFFFFh A0000h 9FFFFh 90000h 8FFFFh Total of 16 64 KByte Blocks 80000h 7FFFFh 70000h 6FFFFh 60000h 5FFFFh 50000h 4FFFFh 40000h 3FFFFh 30000h 2FFFFh 20000h 1FFFFh 10000h 0FFFFh 00000h 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 8 KByte PARAMETER BLOCK 8 KByte PARAMETER BLOCK 32 KByte MAIN BLOCK
FFFFFh FC000h FBFFFh FA000h F9FFFh F8000h F7FFFh F0000h
AI11361
8/43
M29W008ET, M29W008EB
Figure 5. Block Addresses (Bottom Boot Block)
M29W008EB Bottom Boot Block Addresses
1 Summary description
FFFFFh 64 KByte MAIN BLOCK F0000h EFFFFh E0000h DFFFFh D0000h CFFFFh C0000h BFFFFh B0000h AFFFFh A0000h 9FFFFh 90000h 8FFFFh Total of 16 64 KByte Blocks 80000h 7FFFFh 70000h 6FFFFh 60000h 5FFFFh 50000h 4FFFFh 40000h 3FFFFh 30000h 2FFFFh 20000h 1FFFFh 10000h 0FFFFh 00000h 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 0FFFFh 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 64 KByte MAIN BLOCK 32 KByte MAIN BLOCK 8 KByte PARAMETER BLOCK 8 KByte PARAMETER BLOCK 16 KByte BOOT BLOCK 08000h 07FFFh 06000h 05FFFh 04000h 03FFFh 00000h
AI11362
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2 Signal descriptions
M29W008ET, M29W008EB
2
Signal descriptions
See Figure 2: Logic diagram and Table 1: Signal Names, for a brief overview of the signals connected to this device.
2.1
Address Inputs (A0-A19)
The address inputs for the memory array are latched during a Bus Write operation on the falling edge of Chip Enable, E or Write Enable, W. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1 A6, A12 and A15.
2.2
Data Input/Outputs (DQ0-DQ7)
During Bus Write operations, the Data Inputs/Outputs input the data to be programmed in the memory array or a command to be written to the Command Interface. Both are latched on the rising edge of Chip Enable, E or Write Enable, W. The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation, the Electronic Signature (Manufacturer or Device codes), the Block Protection Status or the Data Polling bit (DQ7), Toggle Bits (DQ6) and DQ2), Error bit (DQ5) or Erase Timer bit (DQ3) of the Status Register. Outputs are valid when Chip Enable, E and Output Enable, G are active. The output is high impedance when the chip is deselected or the outputs are disabled and when RP is Low.
2.3
Chip Enable (E)
The Chip Enable, E, activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is High, VIH, the memory is deselected and the power consumption is reduced to the Standby level. The Chip Enable, E, can also be used to control Write operations to the command register and to the memory array, while W remains Low. The Chip Enable must be forced to VID during Block Unprotection operations.
2.4
Output Enable (G)
The Output Enable, G, gates the outputs through the data buffers during a Bus Read operation. When G is High, VIH, the outputs are high impedance. G must be forced to VID during Block Protection and Unprotection operations.
2.5
Write Enable (W)
This Write Enable, W, controls write operations of the memory's Command Interface.
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M29W008ET, M29W008EB
2 Signal descriptions
2.6
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high impedance. See Table 13: Reset/Block Temporary Unprotect AC Characteristics and Figure 13: Reset/Block Temporary Unprotect AC Waveforms. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode.
2.7
Reset/Block Temporary Unprotect Input (RP)
The Reset/Block Temporary Unprotect input, RP, can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been previously protected. A Hardware Reset is achieved by holding RP Low, VIL for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, if the device is in Read or Standby mode, it will be ready for new operations tPHEL after the rising edge of RP. If the device is in Erase, Erase Suspend or Program mode, the Hardware Reset will last tPLYH during which the RB signal will be held at VIL. The end of the memory Hardware Reset will be indicated by the rising edge of RB. A Hardware Reset during an Erase or Program operation will corrupt the data being programmed or the blocks being erased. See Table 13: Reset/Block Temporary Unprotect AC Characteristics and Figure 13: Reset/Block Temporary Unprotect AC Waveforms. Holding RP at VID will temporarily unprotect the previously protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition of RP from VIH to VID must slower than tPHPHH. When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected.
2.8
VCC Supply Voltage
The power supply for all operations (Read, Program and Erase). A 0.1F capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3
2.9
VSS Ground
VSS is the reference for all voltage measurements.
11/43
3 Bus Operations
M29W008ET, M29W008EB
3
Bus Operations
There are 5 standard bus operations that control the device. These are Bus Read, us Write, Output Disable, Standby and Automatic Standby. See Table 2: Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect the bus operations.
3.1
3.1.1
Standard bus operations
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register or the Block Protection Status. Both Chip Enable E and Output Enable G must be Low in order to read the output of the memory. A new Bus Read operation is initiated either on the falling edge of Chip Enable, E, or on any address transition with E at VIL. See Figure 10: Read Mode AC Waveforms, and Table 10: Read AC Characteristics for details of the timing requirements.
3.1.2
Bus Write
Bus Write operations are used to write to the Command Interface or to latch input data to be programmed. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 11 and 12, Write AC Waveforms and Tables 11 and 12, Write AC Characteristics, for details of the timing requirements.
3.1.3
Output Disable
The data outputs are high impedance when the Output Enable G is High with Write Enable W High.
3.1.4
Standby
The memory is in Standby mode when Chip Enable, E, is High and the Program/Erase Controller is idle. The Supply Current is reduced to the Standby Supply Current, ICC2, and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs.
3.1.5
Automatic Standby
If CMOS levels (VCC 0.2V) are used to drive the bus and if the bus is inactive (no address transition, E = VIL) during 150ns or more, the memory automatically enters a Automatic Standby mode where the Supply Current is reduced to the Standby Supply Current, ICC2. The Inputs/Outputs will still output data if a Bus Read operation is in progress.
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M29W008ET, M29W008EB
3 Bus Operations
3.2
Special bus operations
Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.
3.2.1
Read Electronic Signature
The memory has two codes, the Manufacturer code and the Device code, that can be read to identify the memory. These codes allow programming equipment or applications to automatically match their interface to the characteristics of the M29W008E. The electronic Signature is output either by applying the signals listed in Table 2: Bus Operations or by issuing an Auto Select command (see Section 4.2: Auto Select command).
3.2.2
Block Protection and Unprotection
Each block can be individually protected against accidental Program or Erase using programming equipment. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment (Programmer Technique) and the other for in-system use (In-System Technique). Block Protect and Chip Unprotect operations are described in Appendix B: Block protection. Table 2. Bus Operations
Operation Byte Read Byte Write Output Disable Standby Manufacturer Code E VIL VIL VIL G VIL VIH VIH W VIH VIL VIH X(1) VIH RP VIH VIH VIH VIH VIH Address Inputs A0-A19 Cell Address Command Address X X A0= VIL, A1= VIL, A9=VID, others address bits are `Don't Care' A0= VIH, A1= VIL, A9=VID, others address bits are `Don't Care' DQ0DQ7 Data Output Data Input Hi-Z Hi-Z 20h D2h DCh
VIH X(1) VIL VIL
Read Electronic signature Device M29W008ET Code M29W008EB
1. X = VIL or VIH.
VIL
VIL
VIH
VIH
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4 Command interface
M29W008ET, M29W008EB
4
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. All commands start with two coded cycles which unlock the Command Interface. Seven commands are available: Read/Reset, Auto Select (to read the Electronic Signature and the Block Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume (see Table 3: Commands).
4.1
Read/Reset command
The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend.
4.2
Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A13-A19 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/ Outputs DQ0-DQ7, otherwise 00h is output.
4.3
Program command
The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.
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M29W008ET, M29W008EB
4 Command interface
During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 4: Program, Erase Times and Program, Erase Endurance Cycles. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See Section 5: Status register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'.
4.4
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.
4.5
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior.
4.6
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass Mode.
4.7
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50s after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more
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4 Command interface
M29W008ET, M29W008EB
blocks. Each additional block must therefore be selected within 50s of the last block. The 50s timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/ Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical program times are given in Table 4: Program, Erase Times and Program, Erase Endurance Cycles. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to '1'. All previous data in the selected blocks is lost.
4.8
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical program times are given in Table 4: Program, Erase Times and Program, Erase Endurance Cycles. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to '1'. All previous data is lost.
4.9
Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency Time after the Erase Suspend Command is issued (see Table 4: Program, Erase Times and Program, Erase
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M29W008ET, M29W008EB
4 Command interface
Endurance Cycles). Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted.
4.10
Erase Resume Command
The Erase Resume command must be used to restart the Program/Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.
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4 Command interface
M29W008ET, M29W008EB
Table 3.
Commands
Bus Write Operations(2)(3) Length
Command(1)
1st Add Data
2nd Add
3rd
4th
5th Add
6th
7th
Data Add Data Add Data
Data Add Data Add Data
Read/Reset(4)(5)
1 +
X
F0h
Read Memory Array until a new write cycle is initiated. 55h 555h F0h 55h 555h 90h 55h 555h A0h 55h 555h 20h PD 00h 55h 555h 80h 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 55h BA 10h 30h AB
(9) (8)
3 555h AAh 2AAh + 3 555h AAh 2AAh + 4 555h AAh 2AAh 3 555h AAh 2AAh 2 2 X X A0h 90h PA X
Read Memory Array until a new write cycle is initiated. Read Electronic Signature or Block Protection Status until a new write cycle is initiated. (6)(7) PA PD Read Data Polling or Toggle Bit until Program completes.
Auto Select(5) Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Erase Suspend(10) Erase Resume
6 555h AAh 2AAh 6 555h AAh 2AAh + 1 1 X X B0h 30h
30h
Read until Toggle stops, then read all the data needed from any Block(s) not being erased then Resume Erase. Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time.
1. Commands not interpreted in this table will default to read array mode. 2. X = Don't Care. PA = Program Address, PD = Program Data, BA = Block Address, AB = Additional Block. 3. For Coded cycles address inputs A15-A19 are don't care. 4. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new operation (see Table 10: Read AC Characteristics). 5. The first cycles of the Read/Reset and Auto Select commands are followed by read operations. Any number of read cycles can occur after the command cycles. 6. Signature Address bits A0, A1, at VIL will output the Manufacturer Code (20h). Address bits A0 at VIH and A1, at VIL will output the Device Code. 7. Block Protection Address: A0, at VIL, A1 at VIH and A13-A19 within the Block will output the Block Protection status. 8. Read Data Polling, Toggle bits or RB until Erase completes. 9. Optional, Additional Block (AB) addresses must be entered within the erase time-out delay after last write entry, time-out status can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit until Erase has completed or is suspended. 10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
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M29W008ET, M29W008EB
Table 4. Program, Erase Times and Program, Erase Endurance Cycles
Parameter Chip Erase Block Erase (64 KBytes) Erase Suspend Latency Time Program (Byte) Chip Program (Byte by Byte) Program/Erase Cycles (per Block) Data Retention
1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested.
4 Command interface
Min
Typ(1)(2) 12 0.8 15 10 12
Max(2) 60(3) 6(4) 25(3) 200(3) 60(3)
Unit s s s s s cycles years
100,000 20
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. 4. Maximum value measured at worst case conditions for both temperature and VCC.
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5 Status register
M29W008ET, M29W008EB
5
Status register
The status of the Program/Erase Controller during command execution is indicated by bit DQ7 (Data Polling bit), Toggle bits DQ6 and DQ2 and Error bits DQ3 and DQ5. Any attempt to read the memory array during Program or Erase command execution will automatically output these five Status Register bits. The Program/Erase Controller automatically sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked (see Table 5: Status Register Bits).
5.1
Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a '1' during a Bus Read operation within a block being erased. The Data Polling Bit will change from a '0' to a '1' when the Program/ Erase Controller has suspended the Erase operation.
Figure 6: Data Polling Flowchart gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased.
5.2
Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. If any attempt is made to erase a protected block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 100s. If any attempt is made to program a protected block or a suspended block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 1s.
Figure 7: Data Toggle Flowchart gives an example of how to use the Data Toggle bit.
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M29W008ET, M29W008EB
5 Status register
5.3
Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'
5.4
Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to '1'. Before the Program/Erase Controller starts the Erase Timer Bit is set to '0' and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.
5.5
Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.
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5 Status register
M29W008ET, M29W008EB
Table 5.
Status Register Bits
Address Any Address Any Address Any Address Any Address Erasing Block Non-Erasing Block Erasing Block DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1 DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle DQ5 0 0 1 0 0 0 0 0 0 DQ3 - - - 1 0 0 1 1 - DQ2 - - - Toggle Toggle No Toggle Toggle No Toggle Toggle RB 0 0 0 0 0 0 0 0 1 1 No Toggle Toggle 0 0
Operation Program Program During Erase Suspend Program Error Chip Erase Block Erase before timeout Block Erase
Non-Erasing Block Erasing Block Erase Suspend Non-Erasing Block Good Block Address Erase Error Faulty Block Address
Data read as normal 0 0 Toggle Toggle 1 1 1 1
Note:
Figure 6.
Unspecified data bits should be ignored.
Data Polling Flowchart
START
READ DQ5 & DQ7 at VALID ADDRESS
DQ7 = DATA NO NO
YES
DQ5 =1 YES
READ DQ7 at VALID ADDRESS
DQ7 = DATA NO FAIL
YES
PASS
AI03598
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M29W008ET, M29W008EB
Figure 7. Data Toggle Flowchart
START READ DQ6
5 Status register
READ DQ5 & DQ6
DQ6 = TOGGLE YES NO
NO
DQ5 =1 YES READ DQ6 TWICE
DQ6 = TOGGLE YES FAIL
NO
PASS
AI01370C
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6 Maximum rating
M29W008ET, M29W008EB
6
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 6.
Symbol TBIAS TSTG TLEAD VIO(3) VCC VID(3)
Absolute Maximum Ratings
Parameter Temperature Under Bias Storage Temperature Lead Temperature during Soldering(1) Input or Output Voltage Supply Voltage Identification Voltage Value -50 to 125 -65 to 150 260(2) -0.6 to 5 -0.6 to 5 -0.6 to 13.5 Unit C C C V V V
1. Compliant with the ST 7191395 specification for Lead-free soldering processes. 2. Not exceeding 250C for more than 30s, and peaking at 260C. 3. VID and VIO may undershoot to -2V during transition and for less than 20ns during transitions.
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7 DC and AC characteristics
7
DC and AC characteristics
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 7: Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 7.
Operating and AC Measurement Conditions
M29W008E Parameter Min 70 Max 3.6 85 70 30 10 0 to VCC VCC/2 0 to VCC VCC/2 Min 2.7 -40 0 100 10 90 Max 3.6 85 C 70 pF ns V V V Unit
VCC Supply Voltage Ambient Operating Temperature (range 6) Ambient Operating Temperature (range 1) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
2.7 -40 0
Figure 8.
AC Testing Input Output Waveform
VCC VCC/2 0V
AI09444
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7 DC and AC characteristics
M29W008ET, M29W008EB
Figure 9.
AC Testing Load Circuit
0.8V
1N914
3.3k DEVICE UNDER TEST CL
OUT
CL includes JIG capacitance
AI09445
Table 8.
Symbol CIN COUT
Device Capacitance
Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note:
Table 9.
Symbol ILI ILO ICC1 ICC2 ICC3(1) VIL VIH VOL VOH VID IID VLKO(1)
Sampled only, not 100% tested.
DC Characteristics
Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Supply Current (Program or Erase) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CMOS A9 Voltage (Electronic Signature) A9 Current (Electronic Signature) Supply Voltage (Erase and Program lock-out) A9 = VID 1.8 IOL = 1.8mA IOH = -100A VCC -0.4V 11.5 12.5 100 2.3 Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIH, f = 6MHz E = VCC 0.2V RP = VCC 0.2V Program,/ Erase Controller active -0.5 0.7 VCC Min Max 1 1 10 100 Unit
A
A mA A
20 0.8 VCC + 0.3 0.45
mA V V V V V A V
1. Sampled only, not 100% tested.
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M29W008ET, M29W008EB
Figure 10. Read Mode AC Waveforms
7 DC and AC characteristics
tAVAV A0-A19 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7 tGHQX tGHQZ VALID
AI09446
VALID tAXQX
tEHQX tEHQZ
Table 10.
Symbol
Read AC Characteristics
M29W008E Alt Parameter Test Condition 70 90 90 ns E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Unit
tAVAV(1) tAVQV(1) tELQX(2) tELQV(1) tGLQX(2) tGLQV(1) tEHQZ(2) tGHQZ(2) tEHQX tGHQX tAXQX
tRC tACC tLZ tCE tOLZ tOE tHZ tDF
Address Valid to Next Address Valid
Min
70
Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition
Max Min Max Min Max Max Max
70 0 70 0 30 25 25
90 0 90 0 35 30 30
ns ns ns ns ns ns ns
tOH
Min
0
0
ns
1. Address are latched on the falling edge of W, Data is latched on the rising edge of W. 2. Sampled only, not 100% tested.
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7 DC and AC characteristics
M29W008ET, M29W008EB
Figure 11. Write AC Waveforms, W Controlled
tAVAV A0-A19 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ7 VALID tWHDX tWLWH tWHGL tWHEH
VCC tVCHEL RB tWHRL
AI02192
Table 11.
Symbol tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tWHRL(1) tVCHEL
Write AC Characteristics, W Controlled
M29W008E Alt tWC tCS tWP tDS tDH tCH tWPH tAS tAH Parameter 70 Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low tOEH tBUSY tVCS Write Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 70 0 45 45 0 0 30 0 45 0 0 30 50 90 90 0 50 50 0 0 30 0 50 0 0 35 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
1. Sampled only, not 100% tested.
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Figure 12. Write AC Waveforms, E Controlled
tAVAV A0-A19 VALID tELAX tAVEL W tWLEL G tGHEL E tELEH tEHWH
7 DC and AC characteristics
tEHGL
tEHEL tDVEH DQ0-DQ7 VALID tEHDX
VCC tVCHWL RB tEHRL
AI02193
Note:
Address are latched on the falling edge of E, Data is latched on the rising edge of E.
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7 DC and AC characteristics
M29W008ET, M29W008EB
Table 12.
Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tEHRL(1) tVCHWL
Write AC Characteristics, E Controlled
M29W008E Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 70 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low tOEH tBUSY tVCS Chip Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Write Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 70 0 45 45 0 0 30 0 45 0 0 30 50 90 90 0 50 50 0 0 30 0 50 0 0 35 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
1. Sampled only, not 100% tested.
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M29W008ET, M29W008EB
Figure 13. Reset/Block Temporary Unprotect AC Waveforms
7 DC and AC characteristics
W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH
AI09447
Table 13.
Symbol tPHWL(1) tPHEL tPHGL(1) tRHWL(1) tRHEL(1) tRHGL(1) tPLPX tPLYH(1) tPHPHH(1)
Reset/Block Temporary Unprotect AC Characteristics
M29W008E Alt Parameter 70 90 Unit
tRH
RP High to Write Enable Low, Chip Enable Low, Output Enable Low
Min
50
50
ns
tRB
RB High to Write Enable Low, Chip Enable Low, Output Enable Low
Min
0
0
ns
tRP tREADY tVIDR
RP Pulse Width RP Low to Read Mode RP Rise Time to VID
Min Max Min
500 10 500
500 10 500
ns s ns
1. Sampled only, not 100% tested.
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8 Package mechanical
M29W008ET, M29W008EB
8
Package mechanical
Figure 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Note:
Table 14.
Drawing is not to scale.
TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D D1 e E L N 40 0.500 19.800 18.300 - 9.900 0.500 0 0.050 0.950 0.170 0.100 Min Max 1.200 0.150 1.050 0.270 0.210 0.100 20.200 18.500 - 10.100 0.700 5 40 0 1 1 - 0 0 0 0 0 0 0 Typ Min Max 0 0 0 0 0 0 1 1 - 0 0 5 inches
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M29W008ET, M29W008EB
9 Part numbering
9
Table 15.
Example:
Part numbering
Ordering Information Scheme
M29W008ET 70 N 1 E
Device Type M29 Operating Voltage W = 2.7 to 3.6V Device Function 008E = 8 Mbit (1Mb x8), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 70 = 70ns 90 = 90ns Package N = TSOP40: 10 x 20 mm Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel 24mm Packing
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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9 Part numbering
M29W008ET, M29W008EB
Appendix A Block address table
Table 16.
# 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Top Boot Block Addresses, M29W008ET
Size (Kbytes) 16 8 8 32 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range (x8) FC000h-FFFFFh FA000h-FBFFFh F8000h-F9FFFh F0000h-F7FFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 00000h-0FFFFh
Table 17.
# 18 17 16 15 14 13 12 11 10
Bottom Boot Block Addresses, M29W008EB
Size (Kbytes) 64 64 64 64 64 64 64 64 64 Address Range (x8) F0000h-FFFFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh
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9 8 7 6 5 4 3 2 1 0 64 64 64 64 64 64 32 8 8 16 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 08000h-0FFFFh 06000h-07FFFh 04000h-05FFFh 00000h-03FFFh
9 Part numbering
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Appendix B Block protection
Block protection can be used to prevent any operation from modifying the data stored in the Flash. Each Block can be protected individually. Once protected, Program and Erase operations on the block fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. Unlike the Command Interface of the Program/Erase Controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. For example, the techniques for AMD parts will not work on STMicroelectronics parts. Care should be taken when changing drivers for one part to work on another.
9.1
Programmer technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a block follow the flowchart in Figure 15: Programmer Equipment Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. To unprotect the chip follow Figure 16: Programmer Equipment Chip Unprotect Flowchart. Table 18: Programmer Technique Bus Operations, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
9.2
In-System technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the Flash has been fitted to the system. To protect a block follow the flowchart in Figure 17: In-System Equipment Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. To unprotect the chip follow Figure 18: InSystem Equipment Chip Unprotect Flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
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Table 18. Programmer Technique Bus Operations
E G W Address Inputs A0-A18 A9 = VID, A13-A19= Block Address Others = X A9 = VID, A13 = VIH, A16 = VIH Others = X A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A13-A19= Block Address Others = X VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A13-A19= Block Address Others = X
9 Part numbering
Operation
Data Inputs/Outputs DQ7-DQ0 X X Pass = 01h Retry = 00h
Block Protect Chip Unprotect
VIL VID
VID VID
VIL Pulse VIL Pulse
Block Protection Verify
VIL
VIL
VIH
Block Unprotection Verify
Retry = 01h Pass = 00h
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Figure 15. Programmer Equipment Block Protect Flowchart
START
ADDRESS = BLOCK ADDRESS Set-up W = VIH n=0
G, A9 = VID, E = VIL
Wait 4s Protect W = VIL Wait 100s W = VIH E, G = VIH, A0, A6 = VIL, A1 = VIH E = VIL Wait 4s G = VIL Wait 60ns Read DATA
Verify
DATA NO = 01h YES A9 = VIH E, G = VIH End PASS ++n = 25 YES A9 = VIH E, G = VIH FAIL
AI09448
NO
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Figure 16. Programmer Equipment Chip Unprotect Flowchart
START PROTECT ALL BLOCKS Set-up n=0 CURRENT BLOCK = 0
9 Part numbering
A6, A13, A16 = VIH(1) E, G, A9 = VID
Wait 4s Unprotect W = VIL Wait 10ms W = VIH E, G = VIH
ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1, A6 = VIH
E = VIL Wait 4s G = VIL Verify Wait 60ns Read DATA
INCREMENT CURRENT BLOCK
NO
DATA = 00h
YES
NO
++n = 1000 YES
LAST BLOCK YES A9 = VIH E, G = VIH PASS
NO
End
A9 = VIH E, G = VIH FAIL
AI09449
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M29W008ET, M29W008EB
Figure 17. In-System Equipment Block Protect Flowchart
START Set-up n=0 RP = VID WRITE 60h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
Protect
WRITE 60h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
Wait 100s WRITE 40h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Verify
Wait 4s READ DATA ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
DATA NO = 01h YES RP = VIH End ISSUE READ/RESET COMMAND ++n = 25 YES RP = VIH ISSUE READ/RESET COMMAND NO
PASS
FAIL
AI09450
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Figure 18. In-System Equipment Chip Unprotect Flowchart
START PROTECT ALL BLOCKS
Set-up
9 Part numbering
n=0 CURRENT BLOCK = 0
RP = VID WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH
Unprotect
WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH
Wait 10ms
WRITE 40h ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIH
Verify
Wait 4s READ DATA ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIH INCREMENT CURRENT BLOCK
NO
DATA = 00h
YES
NO
++n = 1000 YES RP = VIH
LAST BLOCK YES RP = VIH
NO
End
ISSUE READ/RESET COMMAND
ISSUE READ/RESET COMMAND
FAIL
PASS
AI09451
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10 Revision history
M29W008ET, M29W008EB
10
Table 19.
Date
Revision history
Document Revision History
Version 0.1 First Issue. Revision Details
21-Jun-2005
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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